Structure and method of a column redundancy memory

Details Structure and method of a column redundancy memory Structure and method of a column redundancy memory

2000-09-13

2001-12-04

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S185130, C365S185090, C365S189020

Reexamination Certificate

active

06327197

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates generally to integrated circuits, and more particularly to dynamic random-access memories (DRAMs).
2. Description of Related Art
Networking companies are scrambling in a race to design and develop high performance network processing products for the terabit router market while reducing the cost to implement 10 giga-bits per second/OC192 and above optical carrier network interfaces. Terabit routers demand a fatter throughput of data packets for examining an incoming packet, retrieves a next hop location, and transfers the packet to destination. Memory chips serve as integral components in building a fast network infrastructure. As designers and manufactures attempt to increase the capacity in high-density memory chips, a redundancy memory scheme represents a significant portion in the overall finctionalities of a memory chip.
In a conventional memory, the design is typically rigid in which one redundancy column is dedicated for replacing a particular defective memory column. Such scheme may be too limiting if several memory columns fail, which occur more frequently with high-density memories and wide IO DRAMs. Accordingly, it is desirable to have a memory structure that employs intelligent and flexible column redundancy designs for increasing the overall operations in DRAMs.
SUMMARY OF THE INVENTION
The present invention overcomes the foregoing limitations by disclosing a memory architecture that employs multiple column redundancies which provide multiple options for replacing a defective global odd or even bit line. Each column memory has two multiplexers, one for selecting a global odd bit line and another for selecting a global even bit line. Two or more column redundancies are coupled to each of the multiplexer in the column memory. In a first embodiment, the global odd and even bit lines are connected through odd and even sense amps in a regular column. In a second embodiment, the global odd bit line in a regular column connects through odd sense amps, while the global even bit line in the regular column connects through even sense amps. In a third embodiment, two or more sets of redundancy columns are commonly coupled to a left adjacent regular column and a right adjacent regular column.
Advantageously, the memory structure in the present invention increases the flexibility of column redundancy by n-folds in replacing defective global bit lines. The present invention also advantageously improves yields in the manufacturing of a memory chip, particularly for high-density memory devices.


REFERENCES:
patent: 6134160 (2000-10-01), Waller et al.
patent: 6144591 (2000-11-01), Vlasenko et al.
patent: 6151263 (2000-11-01), Kyung et al.

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