Strobed access semiconductor memory system

Details Strobed access semiconductor memory system Strobed access semiconductor memory system

1984-10-16

1987-05-05

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365193, G11C 700

Patent

active

046637419

ABSTRACT:
An integrated circuit memory system having an array of ECL memory cells, an address circuit, a READ/WRITE circuit and a coupling circuit which increases the operating current of an addressed memory cell during a READ/WRITE operation. The increased operating current is short enough to prevent an excessive saturation of the memory cell transistors. The addressed memory cells remain in a low operating current sufficient to maintain the memory cells in their particular states. Since timing is critical, timing circuits for a system clock are also part of the memory system.

REFERENCES:
patent: 4397001 (1983-08-01), Takemae

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