Stress test mode entry at power up for low/zero power memories

Details Stress test mode entry at power up for low/zero power memories Stress test mode entry at power up for low/zero power memories

1998-10-30

2000-06-27

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

365227, G11C 0007

Patent

active

060814667

ABSTRACT:
A low/zero power memory device includes a deselect mode of operation wherein row decoders, column decoders, write decoders, pre-coders, post-coders and like operational circuits of the memory device needed for wordline and column activation are disabled until such time as a memory device supply voltage exceeds a certain threshold. An included test mode circuit detects test mode activation and overrides application of the power fail deselect mode of operation of the device. This activates the wordline and column related operational circuits immediately at power up such that the device powers up with multiple wordlines and columns activated and ready for application of a stress test overvoltage.

REFERENCES:
patent: 5341336 (1994-08-01), McClure
patent: 5424988 (1995-06-01), McClure et al.
patent: 5644542 (1997-07-01), McClure et al.
patent: 5703512 (1997-12-01), McClure

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