String programmable nonvolatile memory with NOR architecture

Details String programmable nonvolatile memory with NOR architecture String programmable nonvolatile memory with NOR architecture

2005-10-11

2005-10-11

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Sipo/piso

C365S185120, C365S185170, C365S189120, C341S100000

Reexamination Certificate

active

06954395

ABSTRACT:
A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

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