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Method and apparatus for reducing row shut-off time in an interl

Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Patent

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Method and apparatus for reducing worst case power

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement
Reexamination Certificate

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Method and apparatus for reducing write operation time in...

Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate

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Method and apparatus for redundancy word line replacement in a r

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Method and apparatus for redundancy word line replacement in a s

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Method and apparatus for redundant memory configuration in...

Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate

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Method and apparatus for refreshing a dynamic memory

Static information storage and retrieval – Read/write circuit – Data refresh
Patent

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Method and apparatus for refreshing a dynamic random access memo

Static information storage and retrieval – Read/write circuit – Data refresh
Patent

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Method and apparatus for refreshing a semiconductor memory...

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Method and apparatus for refreshing memory cells

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Method and apparatus for refreshing semiconductor memory

Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate

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Method and apparatus for regulating predriver for output buffer

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Method and apparatus for regulating predriver for output buffer

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate

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Method and apparatus for remapping addresses for redundancy

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Method and apparatus for remapping memory addresses for redundan

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Method and apparatus for removal of VT drop in the output diode

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Patent

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Method and apparatus for repair of memory by redundancy

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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Method and apparatus for repairing defective columns of...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Method and apparatus for repairing defective columns of...

Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate

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Method and apparatus for repairing opens on global column lines

Static information storage and retrieval – Read/write circuit – Bad bit
Patent

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