Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2001-08-28
2003-01-21
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230030, C365S230060
Reexamination Certificate
active
06510094
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of, and apparatus for, refreshing semiconductor memory.
2. Discussion of the Related Art
Two of the most common types of RAM cells are static random access memory (SRAM) and dynamic random access memory (DRAM). SRAM cells have a static latching structure that can indefinitely store data so long as power is applied. DRAM cells have storage nodes comprising capacitors and transistors. DRAM cells store data by holding a charge in the capacitors.
Because electric charge leaks out of all capacitors, it is regarded as a characteristic of DRAM that data cannot be stored permanently. The charged storing nodes discharge, therefore DRAM cells need periodic “refreshing” with a new electric charge. The aforementioned periodic refreshing operations are generally performed to each cell a number of times per second to prevent loss of data.
A refresh circuit is used to perform the DRAM refreshing operations. Early DRAMs performed the refresh operations under the control of an external memory device. Recently, most DRAM devices have an internal logic circuit combined with the refresh circuit to perform “internal refreshing operations.” Conventionally, internally refreshing DRAM devices have different external operation conditions from those for SRAMs. Specifically, internally refreshing DRAMs should satisfy at least one of two external operation conditions, (1) a definite write restoration time to be added to the last part of every write cycle and (2) a maximum write cycle time, neither of which are needed for SRAM. An elapsing write restoration time makes the DRAM write access time slower than regular read access time, and a maximum write cycle time imposes a maximum limit to the length of an external write cycle, both conditions imposed to prevent loss of data before refresh.
Despite the refresh requirements, there are a number of advantages that DRAMs have over SRAMs. Among them, DRAM cells are smaller than SRAM cells produced by similar fabricating processes. Reduction of memory cell size reduces production costs while providing larger data storage capacity. Thus, it is preferable to develop DRAMs that can replace SRAMs without imposing additional external operational conditions.
U.S. Pat. No. 4,984,208, issued on Jun. 12, 1989, entitled “Dynamic Read/Write Memory Device Having Better Refresh Operations” discloses a DRAM circuit that can satisfy conditions of write restoration time and maximum cycle time.
An array layout structure of DRAM cells of a conventional DRAM device accessing in a partial word line activation method was disclosed by Takahashi and others in U.S. Pat. No. 6,031,779, issued Feb. 29, 2000, wherein sub-arrays of the memory cells are surrounded with block sense amplifier arrays and sub-word line driver arrays.
FIG. 1
shows a general layout of a refresh-type semiconductor memory device layout as commonly used in the art and as may be used in this invention, if desired. A plurality of memory cell array blocks
40
are divided into n number of row blocks and m number of column blocks, and a plurality of memory sense amplifiers
30
are arranged between the cell array blocks
40
in the direction of rows or bit lines. The block sense amplifiers
30
are shared by two memory cell array blocks
40
, but not for those arranged at both ends of the memory cell array blocks
40
. In the direction of word lines or columns, sub-word line drivers SWD
20
are arranged between the memory cell array blocks
40
in the structure such that two memory cell array blocks
40
share one sub-word line driver
20
. Even though not shown in
FIG. 1
, row and column decoders are arranged in the row and column directions. The row and column decoders designate addresses for specific memory cells.
In the layout structure shown in
FIG. 1
, those block sense amplifiers
30
and sub-word line drivers
20
disposed at the periphery of the layout are not shared, but rather connected only with one memory cell array block
40
. In
FIG. 1
, there are portions of the array where areas accommodating the block sense amplifiers
30
and sub-word line drivers
20
are crossed. The crossed areas are called conjunction areas
50
. Drivers (not shown) are disposed in the conjunction areas
50
to drive the block sense amplifiers
30
.
In the layout structure, after a bit line BL is precharged, a normal word line enable signal NWE and an address coding LSB signal PXi are transmitted to selectively activate one of word lines arranged in the column direction of the array. Then, the selected word line turns on access transistors of the memory cells connected thereto, so as to allow a storing node of each memory cell and a specific bit line connected to the memory cell to share the charge. As a result, the block sense amplifiers
30
sense the activated bit line and then store the sensed data with internal latches. The stored data is passed to an input/output line when a column select line CSL is enabled in response to a column address decoding signal. In this case, if data is not passed to the input/output line because the column select line CSL is not enabled, the data is re-written to a corresponding memory cell during an active restoration process, and a refresh operation is performed while the word line is activated.
In a general architecture of a DRAM device, all memory cells connected to word lines to be enabled can share the electric charge regardless of active restoration or refresh operation. The drivers of the conjunction area
50
(hereinafter, “LA drivers”) should be driven in advance to facilitate data sensing by the block sense amplifiers
30
connected to bit lines of the selected memory cell array blocks. This process requires comparatively large amounts of power. Conventional methods to reduce such power consumption include partial word line activation wherein only a minimum number of word lines and LA drivers are enabled and driven. In other words, column block information signals decoded by column addresses are mixed to enable only word lines corresponding to a memory cell array block
40
whose column select line CSL opens and to drive only a LA driver corresponding to the memory cell array block
40
.
However, there have been problems in application of the partial word line activation method to the DRAM architecture. For example, two memory cell array blocks may share a new charge when a word line is enabled. This is because a SWD array
20
is shared by two memory cell array blocks
40
for purposes of minimizing the size of the DRAM device.
Besides, the other problem is that it is difficult to drive only a LA driver to drive a block sense amplifier commonly connected to two block bit lines because the partial word line activation method accesses in the structure where sub-word line driver
20
and block sense amplifier
30
are shared by memory cell array blocks. In other words, if an output signal ORed by a column block address decoded signal, for instance, a block selection Y (BSY) signal, controls circuits of conjunction areas, only word lines related to the two cell array blocks are activated to drive only a corresponding LA driver that receives an OR output signal, but not other LA drivers of the conjunction areas positioned over and under the driven driver. At this time, there is no problem in the sensing or active restoration process, but at the price of a significant reduction in the total driving capacity of the block sense amplifiers
30
. Consider the situation wherein all block sense amplifiers of a row block whose LA driver is selected are enabled and driven, then other LA drivers of conjunction areas positioned over and under the selected one are not driven when using the partial word line activation method. As a result, the reduction in the driving capacity as such may result in a decrease in the speed of sensing and active restoration of bit lines.
Even if the problems of decreasing the speed of sensing and active restoration processes can be solved by enlarging the size of PMOS and NMOS t
Chung Min-Chul
Han Sang-Jib
Kim Chang-Rae
Park Jong-Yul
Auduong Gene N.
F. Chau & Associates LLP
Nelms David
Samsung Electronics Co,. Ltd.
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