Method and apparatus for reducing row shut-off time in an interl

Details Method and apparatus for reducing row shut-off time in an interl Method and apparatus for reducing row shut-off time in an interl

1996-08-07

1999-11-16

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

36523006, 36523008, G11C 800

Patent

active

059869461

ABSTRACT:
A semiconductor memory includes two pull-down transistors provided at opposite ends of each word line of an interleaved-row array memory. Both of these transistors receive the same global phase signal and are therefore both rendered conductive when a word line is deselected. The two pull-down transistors, acting together, sink sufficient current to rapidly pull down each word line of an interleaved-row array DRAMs, thus minimizing shut-off time.

REFERENCES:
patent: 4719603 (1988-01-01), Shinagawa et al.
patent: 5297104 (1994-03-01), Nakashima
patent: 5311481 (1994-05-01), Casper et al.
patent: 5400283 (1995-03-01), Raad
patent: 5416747 (1995-05-01), Ohira
patent: 5650976 (1997-07-01), McLaury

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