Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-07-15
2001-02-06
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S202000, C365S225700
Reexamination Certificate
active
06185136
ABSTRACT:
TECHNICAL FIELD
The present invention relates to memory devices, particularly dynamic random access memory devices, and, more particularly, to a method and apparatus for preventing defective columns of memory cells from rendering the entire memory device defective.
BACKGROUND OF THE INVENTION
A conventional memory device is illustrated in FIG.
1
. The memory device is a synchronous dynamic random access memory (“SDRAM”)
10
that includes an address register
12
adapted to receive row addresses and column addresses through an address bus
14
. The address bus
14
is generally coupled to a memory controller (not shown in FIG.
1
). Typically, a row address is initially received by the address register
12
and applied to a row address multiplexer
18
. The row address multiplexer
18
couples the row address to a number of components associated with either of two memory bank arrays
20
and
22
depending upon the state of a bank address bit forming part of the row address. The arrays
20
and
22
are comprised of memory cells arranged in rows and columns. Associated with each of the arrays
20
and
22
is a respective row address latch
26
, which stores the row address, and a row decoder
28
, which applies various signals to its respective array
20
or
22
as a function of the stored row address. The row address multiplexer
18
also couples row addresses to the row address latches
26
for the purpose of refreshing the memory cells in the arrays
20
and
22
. The row addresses are generated for refresh purposes by a refresh counter
30
that is controlled by a refresh controller
32
.
After the row address has been applied to the address register
12
and stored in one of the row address latches
26
, a column address is applied to the address register
12
. The address register
12
couples the column address to a column address latch
40
. Depending on the operating mode of the SDRAM
10
, the column address is either coupled through a burst counter
42
to a column address buffer
44
, or to the burst counter
42
, which applies a sequence of column addresses to the column address buffer
44
starting at the column address output by the address register
12
. In either case, the column address buffer
44
applies a column address to a column decoder
48
, which applies various column signals to respective sense amplifiers in associated column circuits
50
for the arrays
20
and
22
.
Data to be read from one of the arrays
20
or
22
are coupled from the arrays
20
or
22
, respectively, to a data bus
58
through the column circuit
50
, and a read data path that includes a data output register
56
. Data to be written to one of the arrays
20
or
22
are coupled from the data bus
58
through a write data path, including a data input register
60
, to one of the column circuits
50
where they are transferred to one of the arrays
20
or
22
, respectively. A mask register
64
may be used to selectively alter the flow of data into and out of the column circuits
50
by, for example, selectively masking data to be read from the arrays
20
and
22
.
The above-described operation of the SDRAM
10
is controlled by a command decoder
68
responsive to high level command signals received on a control bus
70
. These high level command signals, which are typically generated by the memory controller, are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, where the “*” designates the signal as active low. The command decoder
68
generates a sequence of command signals responsive to the high level command signals to carry out a function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
A portion of the column circuits
50
of
FIG. 1
is shown in greater detail in FIG.
2
. The column circuit
50
is shown connected to a pair of arrays
100
,
102
, which may be subarrays in either of the arrays
20
,
22
shown in FIG.
1
. Alternately, a single column circuit
50
containing the circuitry shown in
FIG. 2
may be used to access both of the arrays
20
,
22
shown in FIG.
1
. The column circuit
50
includes a plurality of column node circuits
110
a
-n in addition to a redundant column node circuit
112
. All of these column node circuits
110
,
112
are identical, and, in the interest of clarity and brevity, the internal components of only one column node circuit
110
a
is shown in FIG.
2
.
The column node circuit
110
a
interfaces with two columns of memory cells using two pairs of complementary digit lines D
0
, D
0
* and D
1
, D
1
*, respectively. However, it will be understood that the column node circuit
110
a
may contain fewer or greater numbers of complimentary digit line pairs. In the interest of brevity, the digit lines D
0
, D
0
* and D
1
, D
1
* in the column node circuit
110
as well as in the other column node circuits
110
b
-n,
112
will sometimes be referred to as simply D and D*. Each digit line pair D, D* has coupled therebetween a negative sense amplifier
120
, a positive sense amplifier
122
, an equilibration circuit
124
, and an I/O circuit
126
.
The equilibration circuit
124
is controlled by a precharge control circuit
130
that may be part of the row decoders
28
(
FIG. 1
) to couple the digit lines D, D* to each other and to an equilibration voltage, which typically has a magnitude equal to one-half the magnitude of a supply voltage. The negative sense amplifier
120
and the positive sense amplifier
122
normally receive respective power signals, typically ground potential and either the supply voltage or a pumped voltage having a magnitude that is slightly greater than the magnitude of the supply voltage, respectively. After the digit lines D, D* have been equilibrated by the equilibration circuit
124
, the sense amplifiers
120
,
122
detect a voltage imbalance in the digit lines D, D* during a read access of memory cells in the arrays
100
,
102
. The sense amplifiers
120
,
122
then drive the digit lines D, D* in the direction of the imbalance until one of the digit lines is at the supply voltage and the other of the digit lines is at ground potential.
Once the sense amplifiers
120
,
122
have driven the digit lines D, D* to voltages indicative of the data read from a memory cell in the respective column, the digit lines D, D* are coupled to respective I/O lines I/OA, I/OB* by the I/O circuit
126
. As is a well understood in the art, in a read memory access the signals from the digit lines are coupled to a DC sense amplifier (not shown), which applies a corresponding data signal to the data bus of the memory device. The other digit lines D
1
, D
1
* in the column node circuit
110
a
are similarly coupled to a respective pair of I/O lines I/OB, I/OB* by a respective I/O circuit
126
.
In a write memory access, the I/O lines are driven by respective write drivers (not shown), and are coupled to the digit lines D, D* by the I/O circuit
126
.
The column node circuit
110
a
receives a SEL_R signal from a respective inverter
114
to cause it to couple its digit lines D, D* to the I/O lines I/O, I/O*, respectively. Similarly, the column node circuit
110
b
receives a SEL_R+1 signal to couple its digit lines to the same I/O lines, and the column node circuit
110
n
receives a SEL_R+N signal to couple its digit lines to the same I/O lines. Since the SEL signals select various columns of memory cells in the arrays
100
,
102
, they are normally generated by the column decoder
48
(FIG.
1
).
The I/O circuits
126
in the redundant column node circuit
112
are likewise coupled to the same I/O lines by a select SEL_RED signal, but the SEL_RED signal is generated by a redundant column control circuit
144
. The redundant column control cir
Dorsey & Whitney LLP
Le Vu A.
Micro)n Technology, Inc.
Nguyen Hien
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