Latch and data out driver for memory arrays

Latch circuit operating in synchronization with clock signals

Latch circuit, data output circuit and semiconductor device havi

Latch for storing a data bit and a store incorporating said latc

Latch pulse delay control

Latch scheme with invalid command detector

Latch-based random access memory (LBRAM) tri-state banking...

Latched sense amplifiers as high speed memory in a memory...

Latching circuit for sense amplifier in a DRAM and DRAM utilizin

Line buffer type semiconductor memory device capable of...

Logic array having improved speed characteristics

Logic controlled switch to alternate voltage sources

Look ahead high speed circuitry

Low clock swing latch for dual-supply voltage design

Low current consumption semiconductor memory device

Low power consumption data input/output circuit of embedded...

Low power data latch with overdriven clock signals

Low power memory design with asymmetric bit line driver

Low power SSTL memory controller

Low skew differential receiver with disable feature