Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Patent
1996-11-26
1998-05-05
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
365233, G11C 700
Patent
active
057485410
ABSTRACT:
A latch circuit operating in synchronization with clock signal comprises a memory unit including first and second inverters, the output terminal of the first inverter being connected to the input terminal of the second inverter and the output terminal of the second inverter being connected to the input terminal of the first inverter; a first switching unit coupling the input terminal of the first inverter with the ground; second and third switching units connected together in series and between the ground and the input terminal of the second inverter; a first control unit for controlling the first switching unit according to data signals received from outside; a second control unit for controlling the second switching unit according to the data signals; a delay unit for transmitting, with delay, the signal level at the input terminal of the second inverter, and a third control unit for controlling the third switching unit according to both the clock signals received from outside and the signal levels transmitted through the delay unit.
REFERENCES:
patent: 5073873 (1991-12-01), Nogami
patent: 5491667 (1996-02-01), Sharp
patent: 5568429 (1996-10-01), D'Souza
Mai Son
Mitsubishi Denki & Kabushiki Kaisha
Nelms David C.
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