Low power SSTL memory controller

Details Low power SSTL memory controller Low power SSTL memory controller

2009-01-30

2011-12-13

Dinh, Son (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S063000, C365S230080

Reexamination Certificate

active

08077526

ABSTRACT:
An integrated circuit device having configurable resources is configured as a memory controller that includes a plurality of bi-directional pins, an input buffer circuit that is operable to receive SSTL-compliant input and an output buffer that is operable to generate SSTL-compliant output. The input buffer circuit includes a first single-ended buffer coupled to a first voltage source and to a ground voltage. The first single-ended buffer has an input coupled to one of the bi-directional pins and has an output coupled to the control logic of the memory controller.

REFERENCES:
patent: 6944092 (2005-09-01), Kang
patent: 7315188 (2008-01-01), Wang et al.
patent: 2005/0180235 (2005-08-01), Lee
Ng, Samson, “DDR2 SDRAM Interface for Spartan-3 Generation FPGAs,” XAPP454 (v.2.1), Jan. 20, 2009, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.

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