Latch-based random access memory (LBRAM) tri-state banking...

Details Latch-based random access memory (LBRAM) tri-state banking... Latch-based random access memory (LBRAM) tri-state banking...

2007-09-04

2007-09-04

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189080, C365S230030, C365S230080

Reexamination Certificate

active

11237064

ABSTRACT:
A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state output bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state output bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals. The memory produces an output signal dependent upon the enable signal generation logic output, and thus upon a logic level of the tri-state output bit line.

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