Latching circuit for sense amplifier in a DRAM and DRAM utilizin

Details Latching circuit for sense amplifier in a DRAM and DRAM utilizin Latching circuit for sense amplifier in a DRAM and DRAM utilizin

1990-09-06

1992-08-11

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365205, 365207, 365208, G11C 700

Patent

active

051385775

ABSTRACT:
A latching circuit for sense amplifier in a DRAM for gradually decrease the potential level at the latching point, that is, .phi.S node of N-channel sense amplifying unit of the sense amplifier from the potential level which is lower than that of bit line charging voltage to the potential level of the ground, when a sensing operation of the sense amplifier is enabled, is disclosed. The latching circuit for sense amplifier further comprises a Schmitt trigger circuit for preventing the previous enabling of the sensing operation of the sense amplifier from occurring before data signal from the selected memory cell of the memory cell array apparatus in the DRAM is transferred to 0-bit line B0. A DRAM comprising the latching circuit for sense amplifier and the Schmitt trigger circuit, is also disclosed.

REFERENCES:
patent: 5003513 (1991-03-01), Porter et al.

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