Latch for storing a data bit and a store incorporating said latc

Details Latch for storing a data bit and a store incorporating said latc Latch for storing a data bit and a store incorporating said latc

1984-06-21

1986-05-27

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365154, 365174, G11C 700

Patent

active

045920230

ABSTRACT:
A latch that can serve as a bit storage cell in a random-access store. The latch includes an AND gate (diodes D1 and D2) the input IN of which receives the bit to be stored and the other input of which is connected to a write control line WRL. When no write operation is being performed, transistor T1 is turned off and the state of transistor T2 is dependent on output potential OUT. To perform a write operation, line WRL is activated (goes high) and the state of transistor T3 will depend on the value of the bit applied to input IN. Read operations are performed by means of another AND gate (diodes D4 and D5) and an emitter follower (transistor T4) connected via a bit line BL to an output circuit 2. By adding input transistors and emitter followers to the latch, a multi-port storage can be realized, several rows of which can be simultaneously written into and/or read out.

REFERENCES:
patent: 3504350 (1970-03-01), Stone
H. O. Askin et al., "Glitchless Latch With Extendable Ports to L1 Stage", IBM Technical Disclosure Bulletin, vol. 25, No. 3A, Aug. 1982, pp. 1026-1027.
J. F. Joudinaud et al., "Latch T.sup.2 L Circuit", IBM Technical Disclosure Bulletin, vol. 21, No. 7, Dec. 1978, pp. 2866-2867.

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