Latch and data out driver for memory arrays

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

365190, G11C 700

Patent

active

052395065

ABSTRACT:
A latch and driver circuit is disclosed for use in reading out data from a random access memory cell. The invention, which may be implemented in BICMOS technology, accomplishes high-speed asynchronous latching, level translation and output driving operations. The invention includes a latch and at least one output driver coupled in parallel to a latch driver.

REFERENCES:
patent: 4616342 (1986-10-01), Miyamoto
patent: 4817054 (1989-03-01), Banerjee et al.
patent: 4928265 (1990-05-01), Higuchi et al.

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