Latch scheme with invalid command detector

Details Latch scheme with invalid command detector Latch scheme with invalid command detector

2005-01-04

2005-01-04

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S195000

Reexamination Certificate

active

06839288

ABSTRACT:
Methods and circuits for reducing unnecessary changes to outputs of latch circuits are provided. Unnecessary changes to outputs of latch circuits may be reduced by preventing the outputs of the latch circuits from changing when an invalid command is detected. For some embodiments, an invalid command detector is provided that generates an invalid command signal used to inhibit latch circuits, in response to detecting an invalid command.

REFERENCES:
patent: 5600599 (1997-02-01), Nakayama et al.
patent: 6137744 (2000-10-01), Watanabe
patent: 6307806 (2001-10-01), Tomita et al.
patent: 6477093 (2002-11-01), Okuyama et al.

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