Package map data outputting circuit of semiconductor memory...

Pad for integrated circuit device which allows for multiple...

Partitioned source line architecture for ROM

Passive hierarchical bitline memory architecture which resides i

Pattern layout of transfer transistors employed in a row...

Pattern layout of transfer transistors employed in row decoder

Pattern layout of transfer transistors employed in row decoder

Pattern layout of word line transfer transistors in NAND...

Pattern layout of word line transfer transistors in NAND...

Pattern layout of word line transfer transistors in NAND...

Photon-based memory device and method thereof

Physical memory layout with various sized memory sectors

Pin programmable dram that allows customer to program option des

Plane decoding method and device for three dimensional memories

Portable multiplex bus exerciser

Power interconnect structure for balanced bitline...

Process for manufacturing a phase change memory array in...

Processor-inclusive memory module

Programmable logic integrated circuit devices with low...

Programmable non-volatile data storage circuit and a method...