Pattern layout of word line transfer transistors in NAND...

Details Pattern layout of word line transfer transistors in NAND... Pattern layout of word line transfer transistors in NAND...

2007-02-13

2007-02-13

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S230030

Reexamination Certificate

active

11407146

ABSTRACT:
A semiconductor device includes a memory cell array, word lines, a selector, driving lines and transfer transistors. The memory cell array includes electrically rewritable nonvolatile memory cells. The word lines are commonly connected to memory cells arranged in the same row. The selector configured to select memory cells corresponding to the plurality of word lines in the array. Each driving line is corresponding to one of the word lines. Transfer transistors selectively connect one of the word lines and one of the driving lines. A first word line is connected to a first control gate, a second word line next to the first word line connect to a second control gate, and a third word line next to the second word line connected to a third control gate which is arranged next to first control gate.

REFERENCES:
patent: 6188611 (2001-02-01), Endoh et al.
patent: 6240022 (2001-05-01), Sakui et al.
patent: 6507508 (2003-01-01), Hosono et al.
patent: 6654281 (2003-11-01), Georgakos et al.
patent: 6839283 (2005-01-01), Futatsuyama et al.
patent: 7006383 (2006-02-01), Tanaka
patent: 2006/0007751 (2006-01-01), Tanaka
patent: 11-177071 (1999-07-01), None
patent: 2002-141477 (2002-05-01), None
U.S. Appl. No. 11/227,516, filed Sep. 16, 2005, Tanaka.

Affiliated with

Also associated with

Rating

Pattern layout of word line transfer transistors in NAND... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pattern layout of word line transfer transistors in NAND..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pattern layout of word line transfer transistors in NAND... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3818922