Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2006-06-06
2006-06-06
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S230030
Reexamination Certificate
active
07057915
ABSTRACT:
A semiconductor device includes a memory cell array, first and second selection circuits, and transfer transistors. The first selection circuit selects a block in the memory cell array. The second selection circuit selects several memory cells in the block to erase the memory cells corresponding to word lines in the block. The transfer transistors act as switches that selectively connect, of the word lines and driving lines, word lines and corresponding driving lines for each block. When the word lines are divided into word lines connected to memory cells to be erased and those connected to memory cells not to be erased, the number of transfer transistors connected to the word lines connected to the memory cells to be erased and arranged on both and opposite sides of a transfer transistor of a word line connected to a memory cell not to be erased becomes two or less.
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patent: 2005/0141284 (2005-06-01), Futatsuyama
patent: 11-177071 (1999-07-01), None
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U.S. Appl. No. 11/227,516, filed Sep. 16, 2005, Tanaka.
Kabushiki Kaisha Toshiba
Le Vu A.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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