Partitioned source line architecture for ROM

Details Partitioned source line architecture for ROM Partitioned source line architecture for ROM

2006-04-25

2006-04-25

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S185250, C365S203000, C365S230030

Reexamination Certificate

active

07035129

ABSTRACT:
A partitioned source line architecture for reducing leakage and power in a ROM. In one embodiment, a ROM includes of a plurality of storage cells organized as an array having M rows and N columns. Each column is associated with a precharged source line that is partitioned into a plurality of source line segments based on the number of row banks of the array. A plurality of local source line decoder circuits corresponding to the row banks are provided for decoding a selected source line segment based on the column address as well as a Bank Select signal generated from the row address of a particular cell. Local pull-down circuitry is provided with each bank for deactivating the selected source line segment upon commencing a memory access operation.

REFERENCES:
patent: 5315541 (1994-05-01), Harari et al.
patent: 5526307 (1996-06-01), Yiu et al.
patent: 5600586 (1997-02-01), Lee
patent: 6438064 (2002-08-01), Ooishi

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