Pattern layout of transfer transistors employed in a row...

Details Pattern layout of transfer transistors employed in a row... Pattern layout of transfer transistors employed in a row...

2002-11-26

2004-02-10

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Interconnection arrangements

C365S051000

Reexamination Certificate

active

06690596

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-333719 filed Oct. 31, 2000, the entire contents of which are incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device, and more particularly to the pattern layout of transfer transistors employed in a row decoder, which is used in a nonvolatile memory such as a NAND flash memory.
2. Description of the Related Art
A NAND flash memory is disclosed in, for example, Jin-Ki Kim et al, “A 120 mm
2
64 Mb NAND Flash Memory Achieving 180 ns/Byte Effective Program Speed”, Symposium on VLSI Circuits, Digest of Technical Papers, pp. 168-169, 1996.
FIG. 1
illustrates a pattern layout image of a transfer transistor section provided in the row decoder of the NAND flash memory. The transfer transistor section is used to transfer, to a selected block in a memory cell array, a word-line driving signal and a selected-gate driving signal corresponding to a word line address. For facilitating the drawing and explanation, a case where eight transfer transistors are employed will be taken here as an example.
In the case of
FIG. 1
, the distance between broken lines Yt and Yd is determined from the size of the NAND cell, and transfer transistors Q
0
to Q
7
are arranged in two stages. Each transfer transistor Q
0
to Q
7
is an N channel MOS (NMOS) transistor formed in a p-type substrate, and its source/drain region is sufficiently resistive against a write voltage (program voltage) and an erasure voltage applied thereto.
In the arrangement of the transfer transistors Q
0
to Q
7
shown in
FIG. 1
, when executing programming, 20V+Vth (the threshold voltage of each transfer transistor), 20V, 0V and 10V are applied to the transfer transistors Q
0
to Q
7
, a selected one of word lines WL
0
to WL
7
, each non-selected word line adjacent to the selected one, and the other non-selected word lines, respectively. In this voltage-applied state, when writing data “1” (programming data “1”), a power supply voltage Vdd is applied to a selected bit line, while when writing data “0” (programming data “0”), a ground voltage Vss is applied to the selected bit line.
The biased state assumed when programming data is shown in FIG.
2
. In the case of
FIG. 2
, the word line WL
3
corresponding to a word-line-driving-signal CG
3
is selected. The non-selected word lines adjacent to the selected word line WL
3
are the word lines WL
2
and WL
4
.
In this biased state, the distance X
1
between the transfer transistors Q
2
and Q
3
, to which word-line driving signals CG
2
and CG
3
are supplied, respectively, must be set at a value that enables a leak current, which occurs in a field transistor using the transistor Q
3
as its drain, the transistor Q
2
as its source and the gate
5
as its gate, to be kept not more than a predetermined level. Further, the distance Y
1
between the transfer transistors Q
3
and Q
4
, to which word-line driving signals CG
3
and CG
4
are supplied, respectively, must be set at a value that enables a leak current not more than a predetermined level to occur when 20V has been applied to an n-type diffusion region formed in the p-type substrate between element-isolating regions.
In the case of selecting another word line, the same can be said of each distance X
2
, X
3
and Y
2
to Y
4
.
However, in the above-described pattern layout, if the distance YB is required to be set significantly small so as to satisfy the demand for reduction of memory cell size, the transfer transistors cannot be arranged in two stages, depending upon the distance X
1
or Y
1
that is determined from the device design or process. In this case, a larger number of transfer transistors must be arranged in one stage, which means that the row decoder may have a significantly long length.
As described above, in the conventional semiconductor memory device, transfer transistors, employed in its row decoder for applying a write voltage or an erasure voltage to the control gate of each memory cell, must have a size sufficient to resist the write voltage and the erasure voltage. Moreover, large element-isolating regions are also needed. This being so, the pattern area of the row decoder is inevitably large.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns, the memory cell array having first word lines connected to a first group of memory cells in the plurality of memory cells, second word lines connected to a second group of memory cells in the plurality of memory cells which are adjacent to the first word lines, and third word lines connected to a third group of memory cells in the plurality of memory cells, and a word-line select circuit configured to select at least one row of memory cells from the plurality of memory cells, the word-line select circuit includes a first group, a second group and a third group of word-line select transistors arranged in row and column directions, the first group of word-line select transistors being each connected to an associated one of the first word lines, the second group of word-line select transistors being each connected to an associated one of the second word lines, the third group of word-line select transistors being each connected to an associated one of the third word lines, the third group of word-line select transistors are each interposed between any adjacent two of the first and second group of word-line select transistors.
According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns, the memory cell array having first word lines connected to a first group of memory cells in the plurality of memory cells, second word lines connected to a second group of memory cells in the plurality of memory cells, and third word lines connected to a third group of memory cells in the plurality of memory cells, and a word-line select circuit configured to select at least one row of memory cells from the plurality of memory cells, the memory cell array having first word-line select transistors connected to the first word lines in the memory cell array to select the first word lines, respectively, second word-line select transistors connected to the second word lines to select the second word lines, respectively, and third word-line select transistors connected to the third word lines to select the third word lines, respectively, wherein the first word-line select transistors connected to the first word lines are separated from the third word-line select transistors connected to the third word lines in both the row and column directions, such that a first voltage is applied to the first word lines, a second voltage higher than the first voltage is applied to the second word lines, and a third voltage higher than the second voltage is applied to the third word lines.
According to still another aspect to the present invention, there is provided a semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in rows and columns; and a word-line select circuit including word-line select transistors arranged in row and column directions, and configured to select at least one row of memory cells from the plurality of memory cells, the word-line select circuit including first transistors to which a first voltage is to be applied, second transistors to which a second voltage higher than the first voltage is to be applied, and third transistors to which a third voltage higher than the second voltage is to be applied, the third transistors being separated from the first transistors.


REFERENCES:
patent: 4481609 (1984-11-01), Hiaveril et al.
patent: 5706245 (1998-01-01), Kim
patent: 587514

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