Passive hierarchical bitline memory architecture which resides i

Details Passive hierarchical bitline memory architecture which resides i Passive hierarchical bitline memory architecture which resides i

1993-03-31

1995-10-10

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

365 51, 257211, 257765, H01L 2904

Patent

active

054576474

ABSTRACT:
In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well.

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