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Single feature size MOS technology power device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single feature size MOS technology power device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single mask MIM capacitor and resistor with in trench copper...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single mask scheme method and structure for integrating PMOS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single poly bipolar transistor and method that uses a...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single poly EEPROM with improved coupling ratio

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single poly EPROM cell having smaller size and improved data...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single poly non-volatile memory structure and its...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single poly-emitter PNP using DWELL diffusion in a BiCMOS...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single poly-Si process for DRAM by deep N well (NW) plate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single polysilicon process for DRAM

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single sided buried strap

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single transistor RAM cell and method of manufacture

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single transistor vertical memory gain cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single transistor vertical memory gain cell

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single wafer thermal CVD processes for hemispherical grained...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single wafer thermal CVD processes for hemispherical grained...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single-chip contact-less read-only memory (ROM) device and...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single-electron device including therein nanocrystals

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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Single-pole component manufacturing

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
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