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Algorithm to test LPAR I/O subsystem's adherence to LPAR I/O...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate

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Algorithmic pattern generator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Algorithmic pattern generator for integrated circuit tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Algorithmic test pattern generator, with built-in-self-test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Algorithmically programmable memory tester with breakpoint...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Algorithmically programmable memory tester with history...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Algorithmically programmable memory tester with test sites...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Alignment of recovered clock with data signal

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Allocating data bursts and supporting hybrid auto...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Allocation of sparing resources in a magnetoresistive...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate

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Almost full-scan BIST method and system having higher fault...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Altering a degree of redundancy used during execution of an...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Altering bit sequences to contain predetermined patterns

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Alternate fault handler

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Alternate port apparatus for manufacturing test of...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Alternate routing of management message to simplified network el

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent

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Alternating current built in self test (AC BIST) with...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate

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Alternative path control system and method

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Ameliorating the adverse impact of burst errors on the...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Amplifying magnitude metric of received signals during...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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