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Apparatus and method for generating addresses in a built-in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for generating addresses in a SRAM built-in

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Apparatus and method for generating an error signal

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Apparatus and method for generating block code in a mobile...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatus and method for generating codes in a communication...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatus and method for generating codes in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatus and method for generating codes in communication...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatus and method for generating codes in communications...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatus and method for generating error detection codes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Apparatus and method for generating interleave erasure...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatus and method for generating sub-codes to a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatus and method for hardware-assisted diagnosis of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for header decompression

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatus and method for header decompression

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatus and method for high speed sampling or testing of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for high-speed SAS link protocol testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for high-speed SAS link protocol testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Apparatus and method for hybrid detection of memory data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Apparatus and method for hybrid pin control of boundary scan app

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Apparatus and method for ideal value estimation in an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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