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Register selection circuitry receiving select signals from...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Reinstate apparatus and method to recreate data background...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Relative dynamic skew compensation of parallel data lines

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Relative position and/or posture measuring system for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Relative position and/or posture measuring system for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Relay device and corresponding method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Relay station for wireless communication traffic

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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Relay transmission method and system, and device used thereof

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Relay-assisted HARQ transmission system

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Reliability monitor for a memory array

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Reliability-based type-II hybrid ARQ scheme

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Reliable communication between multi-processor clusters of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Reliable message transmission with packet-level resend

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Reliable method and system for efficiently transporting...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Reliable wafer-scale integrated computing systems

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Relocatable storage protect keys for system main memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Relocating unreliable disk sectors when encountering disk...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Relocating unreliable disk sectors when encountering disk...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Remote BIST high speed test and redundancy calculation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Remote BIST high speed test and redundancy calculation

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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