Relative dynamic skew compensation of parallel data lines

Details Relative dynamic skew compensation of parallel data lines Relative dynamic skew compensation of parallel data lines

2005-06-14

2005-06-14

DeCady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Skew detection correction

C713S503000

Reexamination Certificate

active

06907552

ABSTRACT:
A system performs a two-step skew compensation procedure by first correcting for any phase error alignment between a parallel link clock and data signal edges of each data channel, thereby allowing the received data bits to be correctly sampled. Then, a second step is performed to “word-align” the bits into the original format, which is accomplished with a Skew Synchronizing Marker (SSM) byte in a data FIFO of each data channel. The SSM byte is transmitted on each data channel and terminates the skew compensation procedure. When the SSM byte is detected by logic in the data FIFO of each data channel, the data FIFO employs the SSM byte to initialize the read and write pointers to properly align the output data.

REFERENCES:
patent: 5513377 (1996-04-01), Capowski et al.
patent: 6031847 (2000-02-01), Collins et al.
patent: 6636993 (2003-10-01), Koyanagi et al.

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