Synchronous clocked full-rail differential logic with...
Synchronous contention prevention logic for bi-directional signa
Synchronous differential logic system for hyperfrequency operati
Synchronous dual port RAM
Synchronous dual word decoding using PLA
Synchronous first-in/first-out block memory for a field...
Synchronous first-in/first-out block memory for a field...
Synchronous first-in/first-out block memory for a field...
Synchronous first-in/first-out block memory for a field...
Synchronous first-in/first-out block memory for a field...
Synchronous integrated circuit device utilizing an...
Synchronous memory
Synchronous self-timed clock pulse circuit having improved power
Synthesis-friendly FPGA architecture with variable length and va
System and apparatus of reconfigurable transceiver design...
System and method for a high speed, bi-directional, zero...
System and method for a switched data bus termination
System and method for adjusting a voltage
System and method for asynchronous dual bus conversion using dou
System and method for balancing capacitively coupled signal...