Synchronous contention prevention logic for bi-directional signa

Details Synchronous contention prevention logic for bi-directional signa Synchronous contention prevention logic for bi-directional signa

1996-06-28

1998-06-16

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 26, 326 37, 326 82, 395728, H03K 190175, G06F 1320

Patent

active

057677018

ABSTRACT:
A synchronous contention prevention circuit for a bi-directional bus. The synchronous contention prevention circuit comprises a synchronous anticontention circuit coupled to a first input/output circuit. The synchronous anticontention circuit receives a driver select signal and a clock signal. The first input/output circuit has a first input coupled to the synchronous anticontention circuit and a first output. When the driver select signal is in a first logic state, the first input/output circuit is disabled from driving the first output. Subsequently, the driver select signal transitions from the first logic state to a second logic state. After the driver select signal transition to the second logic state, the synchronous anticontention circuit generates a first signal in response to a first transition of the clock signal. The synchronous anticontention circuit then generates a second signal in response to the first signal and a second transition of the clock signal. The second signal enables the first input/output circuit to drive the first output. The first output may be coupled to a bi-directional bus.

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