Synchronous dual word decoding using PLA

Details Synchronous dual word decoding using PLA Synchronous dual word decoding using PLA

1994-03-13

1995-08-29

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326 45, H03M 738, H03K 19084

Patent

active

054464013

ABSTRACT:
A logic circuit arrangement for performing synchronous dual word decoding utilizing a programmable logic array which is formed with a reduced number of transistor counts. This is achieved by organizing the AND plane (64) so as to decode only the seven (7) most significant bits of an 8-bit opcode word. A LSB decoder circuit (153) is used for decoding the least significant bit of the opcode word separately and outside of the AND plane. As a result, the amount I.C. chip space required has been substantially reduced.

REFERENCES:
patent: 4477739 (1984-10-01), Proebsting et al.
patent: 4641286 (1987-02-01), Shimotori et al.
patent: 4899315 (1990-02-01), Houston
patent: 5257229 (1993-10-01), McClure et al.
patent: 5262994 (1993-11-01), McClure

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