Synchronous memory

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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Details

C326S093000, C365S230050

Reexamination Certificate

active

11041319

ABSTRACT:
Systems and methods are disclosed herein to provide improved memory techniques for logic blocks within a programmable logic device. For example, in accordance with an embodiment of the present invention, a programmable logic device includes a first and a second logic slice adapted to receive a first and a second clock signal. The first and second logic slices may be combined to form wider and deeper memory and single port or synchronous dual port memory.

REFERENCES:
patent: 4942593 (1990-07-01), Whiteside et al.
patent: 6091645 (2000-07-01), Iadanza
patent: 6185119 (2001-02-01), Haeberli et al.
patent: 6411124 (2002-06-01), Lee et al.
patent: 6671842 (2003-12-01), Phan et al.
patent: 6987401 (2006-01-01), Langhammer et al.

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