Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1998-10-01
2001-03-13
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S098000
Reexamination Certificate
active
06201413
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates, in general, to the field of integrated circuit (“IC”) devices. More particularly, the present invention relates to a technique for integrating the internal clock signal and functional commands in IC devices utilizing an externally supplied clock signal and requiring a positive set-up time to discern and/or execute commands. The technique of the present invention is especially advantageous when implemented in conjunction with memory ICs, including synchronous dynamic random access memory (“SDRAM”) devices.
In many integrated circuit devices utilizing an externally supplied clocking signal, a relatively large clock buffer is typically utilized to amplify, or “buffer”, the signal to then drive a derivative internal clock signal which is routed to various of the IC's command executing portions. Commands directing the IC to then execute a specific function are then compared against the internal clock signal and executed if the resultant logic is correct. This is an inherently slow process inasmuch as the clock must first be “buffered up” (i.e. amplified) in order to drive the relatively large capacitance of the on-chip clock network with more speed reducing gate delays being added in ultimately deciding which commands to execute.
SUMMARY OF THE INVENTION
The technique of the present invention is of especial utility in achieving overall faster device speed by integrating the clock signal with the various executable commands to an IC device as soon as possible to create a parallel set of clock command signals. In this way, the clock signal itself is integrated with the commands eliminating the necessity of providing a “main clock” signal routed internally throughout the chip. As a consequence, all of the commands generated in this way are, in fact, clock signals as well. That is, they each have the same rising (or falling) edge time, duty cycle and duration as that previously provided by a typically generated internal clock function.
Importantly, generating the commands early and integrating them with the clock signal itself results in a much decreased loading on the device internal clock line where, typically, only one command can be generated on a given cycle. Consequently, the integration of the clock and command signals shares as much drive power as possible between the commands resulting in substantial integrated circuit die area and device power savings.
Through the use of the technique of the present invention, overall faster execution of commands is achieved thereby affording faster data access times in integrated circuit memory applications. Concomitantly, this faster execution time allows lower performance (i.e. less expensive) process technologies to be used to achieve comparable overall performance targets. Still further, since all commands are now inherently synchronized as to their rise time and duration (and hence, their fall time), a number of internal “race” conditions are obviated which might otherwise potentially lead to device logic errors.
Particularly disclosed herein is an integrated circuit which comprises an external clock pad for receiving an input clock signal and a clock buffer for buffering the input clock signal and providing a buffered clock signal at an output thereof. The integrated circuit further comprises a reset circuit coupled to the output of the clock buffer for delaying the buffered clock signal to produce a delayed clock signal and at least one selectively enablable command logic circuit operative in response to the buffered clock signal and the delayed clock signal to provide a clock command signal having a first state thereof initiated on a first logic level transition of the buffered clock signal and a second state thereof initiated on an opposite second logic level transition of the delayed clock signal.
Further disclosed herein is a process for integrating an internal clock signal with a number of functional commands in an integrated circuit device. The process comprises: providing an external clock signal to the device; buffering the external clock signal to provide an internal clock signal having n gate delays; delaying the internal clock signal to provide an internal reset signal having n+1 additional gate delays; and utilizing the internal clock and reset signals in conjunction with a selected one of a number of enable signals to cause a corresponding one of the functional commands to transition to a first signal level thereof when the internal clock and reset signals are both in a first state thereof and to transition to a second signal level thereof when the reset signal transitions to a second state thereof.
Also further disclosed herein is a process for implementing functional commands in an integrated circuit device. The process comprises: supplying an external clock signal to the integrated circuit device; buffering the external clock signal to provide a buffered clock signal; deriving a delayed clock signal corresponding to the buffered clock signal; combining the buffered clock signal and the delayed clock signal to provide a clock command signal having a first state thereof initiated on a selected transition of the buffered clock signal and having a second state thereof initiated on an opposite transition of the delayed clock signal; and routing the clock command signal to command executing portions of the integrated circuit device in lieu of the buffered clock signal.
REFERENCES:
patent: 5801559 (1998-09-01), Sawai et al.
patent: 6049241 (2000-04-01), Brown et al.
patent: 6084453 (2000-07-01), Fuse et al.
Hogan & Hartson LLP
Kubida William J.
Le Don Phu
Tokar Michael
United Memories Inc.
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