Search
Selected: M

Method and apparatus for providing a non-volatile...

Electronic digital logic circuitry – Multifunctional or programmable – Field-effect transistor
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for providing a non-volatile...

Electronic digital logic circuitry – Multifunctional or programmable – Field-effect transistor
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for providing a preselected voltage to...

Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for providing a scheduler select...

Electronic digital logic circuitry – Multifunctional or programmable
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for providing clock signals to macrocells o

Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for providing security for debug circuitry

Electronic digital logic circuitry – With test facilitating feature
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for pulsed clock tri-state control

Electronic digital logic circuitry – Tri-state
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for ratioed logic structure that uses...

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing back-to-back voltage...

Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing bipolar current effects in...

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing bus noise and power consumptio

Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing clock enable setup time in...

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing clock-data skew by clock shift

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing coupling switching noise in in

Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing dynamic programmable logic...

Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing induced switching transients

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Patent

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing induced switching transients

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing induced switching transients

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing leakage in dynamic...

Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Method and apparatus for reducing leakage in integrated...

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate

  [ 0.00 ] – not rated yet Voters 0   Comments 0
  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.