Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2000-07-31
2001-09-11
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S014000, C326S015000, C326S095000, C327S427000, C327S534000, C327S566000
Reexamination Certificate
active
06288572
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to digital integrated circuits, and more particularly to dynamic logic circuits implemented in Silicon-On-Insulator (SOI) technology with enhancements that reduce leakage current within the circuits.
2. Description of the Related Art
Dynamic logic circuits are widely used in integrated circuit designs, especially in Very Large Scale Integrated (VLSI) circuit designs. Because dynamic logic circuits use comparably fewer transistors per circuit block than static logic circuits, dynamic logic circuits have relatively higher circuit densities and are very desirable for use in VLSI circuits such as microprocessors and memories.
Complementary Metal Oxide Semiconductor (CMOS) technology has been the technology of choice for low power designs, because the bulk of the power dissipation in CMOS circuits occurs when the transistors are switching. This characteristic has made CMOS implementations preferable for low power static designs. CMOS static circuits use P-channel and N-channel MOS devices in a complementary configuration to form logic gates.
Dynamic circuits are typically not complementary designs, as the P-channel devices and the N-channel devices are used to perform different functions within a logic gate. For example a p-channel transistor is used to pre-charge an evaluation node, and an n-channel transistor is used to discharge the node in response to logic inputs.
Silicon-On-Insulator (SOI) technology is a relatively new technology having enhanced low power characteristics, which makes it ideal for implementing low power dynamic gates. Additionally, SOI technology has less parasitic substrate capacitance, which leads to a higher switching speed for transistors implemented in SOI. Rather than embedding the channel material in a semiconductor substrate, SOI fabrication technology forms channel material on top of an oxide layer, decreasing leakage resistance and parasitic capacitance. SOI devices are isolated by Shallow Trench Insulation (STI), rather than the substrate, which further reduces capacitive effects and noise coupling from other devices.
There is a drawback associated with transistors formed in SOI technology, however. A parasitic bipolar transistor exists in both non-insulated MOS implementations and the SOI implementation. The bipolar transistor has an emitter and collector formed by the doped regions at the two ends of the channel (N+ material for an N-channel MOS transistor). The base of the transistor is formed by the substrate. In non-insulated MOS technology, the substrate is typically biased so that the transistor will always be off. For N-channel material, this bias is accomplished by connecting the substrate to the lowest negative potential in the circuit. In SOI implementations, because the channel material is deposited on an insulator, the body of the MOS transistor has no electrical connection. This is known as the “floating-body effect,” and can cause malfunction of dynamic gates implemented in SOI technology. The floating-body effect causes pre-charge leakage by lowering the threshold of the transistors in logic input ladders, since the body of the transistor contributes to the overall field in the channel of the transistor. The floating-body effect decreases the noise immunity of a dynamic logic gate, as well as increasing the sensitivity to coupling from other input signals and sub-threshold variations in voltages at the gate's logic inputs. The floating-body effect can be overcome by “contacting” the body by connecting the body to an appropriate power supply potential, but this increases the capacitance of the device and the contact itself contributes a resistor-capacitor (RC) time constant due to the resistance of the contact.
It would therefore be desirable to implement dynamic logic circuits in such a way that the floating-body effect can be reduced or eliminated.
SUMMARY OF THE INVENTION
The objective of reducing the leakage and threshold lowering in Silicon-On-Insulator (SOI) dynamic logic gates is accomplished in a dynamic logic gate that includes a pre-charge transistor, one or more logic ladders having multiple logic inputs, a bias generator for generating a negative bias and a bias control for applying a bias generator output to intermediate nodes of the logic ladders when a pre-charge signal is active. The bias generator may be driven by the pre-charge input signal by using a delayed bootstrap circuit that charges a capacitor and shifts the level at the positively charged capacitor terminal to ground. The bootstrap circuit produces a negative potential at the other terminal that can be applied as a negative bias to the logic ladders.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 6049230 (2000-04-01), Durham et al.
patent: 6094072 (2000-07-01), Davies et al.
patent: 6150834 (2000-11-01), Ciraula et al.
patent: 6150869 (2000-11-01), Storino et al.
patent: 6163173 (2000-12-01), Storino et al.
patent: 6188247 (2001-02-01), Storino et al.
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Salys Casimer K.
Tan Vibol
Tokar Michael
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