Method and apparatus for providing security for debug circuitry

Details Method and apparatus for providing security for debug circuitry Method and apparatus for providing security for debug circuitry

2007-07-24

2007-07-24

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

With test facilitating feature

C714S724000, C713S168000

Reexamination Certificate

active

10638795

ABSTRACT:
The invention relates to debug circuitry (20) and more particularly to a method and apparatus for providing security for debug circuitry (20). In one embodiment, a plurality of non-volatile elements (38) are used in providing selective disabling and re-enabling of at least a portion of the debug circuitry (20). Authentication may also be used. The present invention may use any debug interface, including standard debug interfaces such as the JTAG debug interface defined by the IEEE.

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patent: 2003/0014653 (2003-01-01), Moller et al.
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patent: 2004/0123118 (2004-06-01), Dahan et al.

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