Method and apparatus for providing a scheduler select...

Details Method and apparatus for providing a scheduler select... Method and apparatus for providing a scheduler select...

2007-11-27

2007-11-27

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

C326S038000, C326S041000

Reexamination Certificate

active

11250944

ABSTRACT:
Method and apparatus for providing a scheduler select multiplexer is described. In one example, a multiplexer is provided having a plurality of input ports in respective communication with a plurality of queues, an output port, and a select port. A scheduler is provided to execute a scheduling algorithm to periodically generate a schedule comprising a set of entries. Each of the entries comprises at least one bit for controlling the select port of the multiplexer. A memory is provided to store the schedule. For each of a plurality of clock cycles, the select port of the multiplexer is driven with one of the entries such that the multiplexer sends data from one of the plurality of queues to the output port.

REFERENCES:
patent: 6396853 (2002-05-01), Humphrey et al.
patent: 2003/0058869 (2003-03-01), Novick
Harteros, Kostas G.I., “Fast Parallel Comparison Circuits for Scheduling”, Technical Report Forth-ICS/TR-304, Inst. of Computer Science, Forth, Heraklio, Crete, Greece; M. Sc. Thesis, Univ. http://archvlsi.forth.gr/muqpro/heapMgt.html.
Ioannou, A.; Katevenis, M., “Pipelined Heap (Priority Queue) Management for Advanced Scheduling in High Speed Networks”, Proc. IEEE Int. Conf. on Communications (ICCC'2001), Helsinki, Finland, Jun. 2001, pp. 2043-2047; http://archvlsi.ics.forth.gr/muqpro/heapMgt.html.

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