Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-03-31
2003-01-14
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S068000, C326S086000
Reexamination Certificate
active
06507218
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of improving signal integrity on a high speed data bus.
BACKGROUND OF THE INVENTION
The response of a high-speed data bus, such as one of today's high bandwidth memory busses, depends strongly on the characteristics of the output drivers coupled to the bus. Among the various characteristics that affect signal integrity on the data bus is the voltage at which the output driver becomes a non-linear current source. This non-linearity can negatively impact signal integrity and can result in data corruption.
FIG. 1
shows a prior data bus coupled to a bus controller
170
. The bus controller
170
may be connected to a microprocessor or other computer system agent (not shown). The data bus is represented by transmission line segments
120
,
130
, and
140
. The bus is terminated by a terminating resistor
110
which is tied to a terminating voltage Vterm. Coupled to the bus are two driver transistors
150
and
160
. The driver transistor
150
may receive an input signal at its gate terminal
151
and the driver transistor
160
may receive another input signal at its gate terminal
161
. The input signals may be received from a memory device or other data source. The driver transistors
150
and
160
serve to transmit data out onto the data bus.
The driver transistors
150
and
160
conduct current when a logically high voltage is applied to the gate terminals of the driver transistors. The bus controller
170
detects the current drain through the driver transistors
150
and
160
and in this manner the driver transistors
150
and
160
are able to communicate with the bus controller
170
. The bus controller
170
has a minimum current specification that must be met before the bus controller
170
can detect data transmission from the driver transistors
150
and
160
. A typical current specification may be 28 mA. Therefore, for this example, the driver transistors
150
and
160
must be able to sink 28 mA of current in order to ensure proper data transfer.
A problem may occur when driver transistors
150
and
160
try to perform a back-to-back transfer. For this example, Vterm equals 1.8V and the logically high voltage applied to the gate terminal of the driver transistors
150
and
160
is also 1.8V. When 1.8 volts is present on the bus (due to the connection to Vterm through the terminating resistor
110
) and a logically high voltage is applied to the gate terminals of the driver transistors
150
and
160
, the driver transistors
150
and
160
operate in their saturation regions and the driver transistors
150
and
160
are therefore able to sink a constant current (28 mA is this example). If, however, the voltage on the bus falls below the driver saturation voltage, then the driver transistors
150
and
160
would not be operating in their saturation regions and would therefore not be able to sink a constant current of 28 mA. This can present problems during back-to-back transfers.
For example, a logically high voltage is applied to the gate terminal
151
of the driver transistor
150
during a clock period and the driver transistor
150
sinks 28 mA during that clock period. Towards the end of the clock period, the logically high voltage is removed from the gate terminal of the driver transistor
150
and the driver transistor
150
ceases to sink current. In the next clock period, another logically high voltage is applied to the gate terminal
161
of driver transistor
160
. However, instead of 1.8V being present on the bus at the beginning of the clock period, the data transfer during the previous clock period may have caused the voltage on the bus to drop to perhaps 1.0V. With a logically high voltage of 1.8V applied to the gate terminal
161
and with the bus sitting at 1.0V, the driver transistor
160
is not able to operate in its saturation region and is not able to sink a constant 28 mA. Data corruption is a possible result.
Prior data bus systems have dealt with this problem by inserting a wait cycle between data transfers. For example, with the data transfer described above an extra clock period can be inserted between the data transfer of driver
150
and the data transfer of driver
160
, thus allowing the voltage on the data bus time to return to 1.8V which would allow the driver transistor
160
to operate in its saturation region. The insertion of a wait cycle, however, has the drawback of reducing data throughput and negatively impacting system performance.
REFERENCES:
patent: 5128560 (1992-07-01), Chern et al.
patent: 5179299 (1993-01-01), Tipon
patent: 5235222 (1993-08-01), Kondoh et al.
patent: 5781034 (1998-07-01), Rees et al.
patent: 5969554 (1999-10-01), Chan et al.
patent: 6031395 (2000-02-01), Choi et al.
patent: 6040737 (2000-03-01), Ranjan et al.
patent: 6184700 (2001-02-01), Morris
Copy of Search Report for PCT/US01/08067, mailed Sep. 10, 2001, 2 pages.
Hsu Jen-Tai
To Hing Y.
Intel Corporation
Tokar Michael
Tran Anh Q.
Wells Calvin E.
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