Electronic digital logic circuitry – Tri-state
Reexamination Certificate
2000-06-30
2002-02-12
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Tri-state
C326S057000, C326S058000, C326S086000, C327S112000
Reexamination Certificate
active
06346828
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to tri-state bus arbitration, and specifically to the control of tri-state bus drivers and receivers.
BACKGROUND OF THE INVENTION
A bus is a set of wires or metal traces designed to transfer all bits of a data word, address or control signal from a specified source to a destination. A bus may be unidirectional (i.e. one way communication) or bi-directional (i.e. two way communication). Additionally, a bus may be dedicated or shared. A dedicated bus is a bus with a unique source and destination. A shared bus is a bus which connects one of several sources with one of several destinations. A disadvantage to dedicated busses is that multiple dedicated buses may be necessary for coupling multiple sources and destinations together. As the bus widths increase to handle greater amounts of data in parallel, the number of wires or metal traces increase which can use significant area within an integrated circuit or printed circuit board.
One type of bi-directional shared bus is a tri-state bus. A tri-state bus is a localized network bus and is used to efficiently route data, address and or control signals over a single set of bus wires. Multiple tri-state bus drivers and receivers (such as latches or registers) are coupled to the tri-state bus in order to share it to route signals from one of a plurality of sources to one or more of a plurality of destinations. As a result of the multiple tri-state drivers and receivers sharing a single bus, bus arbitration is important. Bus arbitration of a tri-state bus includes the enable timing of tri-state drivers driving the tri-state bus and the clocking of receivers coupled to the tri-state bus. While multiple receivers may be listening to receive information off a tri-state bus at the same time, only one driver should be driving the tri-state bus at a time in order to avoid excessive power consumption, false signals, and possible circuit damage. Therefore, the tri-state bus is time shared by the tri-state drivers (i.e. sources) and the receivers (i.e. destinations) in order to avoid bus contention or collisions. The communication between tri-state drivers and receivers can be asynchronous or synchronous. In a synchronous system the drivers and receivers communicate between each other at known periods of time and are usually synchronized together by using the same clock source. Asynchronous systems have communication at any time and usually include a control signal, a flag or a destination address with the information being transferred so that the destination can determine that it needs to receive the information being transferred. Asynchronous systems are often employed where the data transmission time periods are different from sources to destinations over the bus. Synchronous system are often employed where the data transmission time period is to be substantially the same between sources and destinations.
Tri-state drivers, also refereed to as three state buffers, are well known. Tri-state inverters or three state inverters are similar to tri-state drivers but have a logical inversion from input to output. Tri-state drivers and inverters typically have three output states, a high level (logical one), a low level (logical zero) and a high impedance state (logically referred to as a Z or unknown state). The output of tri-state drivers and inverters when enabled actively drive a tri-state bus to a high level or a low level. When disabled, the output of tri-state drivers and inverters are not actively driving the tri-state bus and are in a high impedance state. In the high impedance state the output resistance of the tri-state buffer and inverter when looking into the output is ideally infinite. In reality there is typically some leakage current associated with the output stage of the tri-state buffer or inverter such that they have a relatively high finite amount of impedance.
With the increase in system clock frequencies to improve system performance, bus arbitration timing has become more important in order to accommodate increasing clock frequencies. It is desirable to provide an improved tri-state control method and apparatus to provide improved bus arbitration timing for increased system performance.
REFERENCES:
patent: 4257095 (1981-03-01), Nadir
patent: 4761647 (1988-08-01), Hallenbeck et al.
patent: 5021684 (1991-06-01), Ahuja et al.
patent: 5216289 (1993-06-01), Hahn et al.
patent: 5381059 (1995-01-01), Douglas
patent: 5398000 (1995-03-01), Wu
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5455957 (1995-10-01), Pawlowski et al.
patent: 5497114 (1996-03-01), Shimozono et al.
patent: 5500817 (1996-03-01), McLaury
patent: 5537640 (1996-07-01), Pawlowski et al.
patent: 5557225 (1996-09-01), Denham et al.
patent: 5617362 (1997-04-01), Mori et al.
patent: 5701447 (1997-12-01), Hahn
patent: 5721875 (1998-02-01), Fletcher et al.
patent: 5757217 (1998-05-01), Thompson
patent: 5793672 (1998-08-01), Wong et al.
patent: 5799161 (1998-08-01), Merrick
patent: 5845107 (1998-12-01), Fisch et al.
patent: 5900744 (1999-05-01), Bisen et al.
patent: 5986473 (1999-11-01), Krishnamurthy et al.
patent: 6028448 (2000-02-01), Landry
patent: 6078980 (2000-06-01), Holland et al.
patent: 6111898 (2000-08-01), Banik et al.
patent: 6175253 (2001-01-01), Maiyuran et al.
patent: 362090020 (1987-04-01), None
Hayes, Computer Architecture and Organization, 1978, pp. 103-104 & 401-418, McGraw-Hill Book Company.
Millman, MicroElectronics—Digital and Analog Circuits and Systems, 1979, pp. 151-152 & 632-635, McGraw-Hill Book Company.
Mano, Digital Logic and Computer Design, 1979, pp. 576-578, Prentice-Hall, Englewood Cliffs, NJ.
Fletcher Thomas D.
Rosen Eitan
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Paik Steven S.
Tokar Michael
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