Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2007-10-09
2007-10-09
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S098000, C327S291000
Reexamination Certificate
active
11371380
ABSTRACT:
A multi-enabled clock gating circuit reduces clock enable setup time. In one example, the multi-enabled clock gating circuit comprises an OAI logic gate and a clock enable control circuit. The OAI logic gate is configured to generate a gated clock signal by inverting an input clock signal responsive to one of a timing-sensitive clock enable signal and a timing-insensitive clock enable signal being active. The clock enable control circuit is configured to prevent the OAI logic gate from receiving the timing-insensitive clock enable signal responsive to the timing-sensitive clock enable signal being active. In one or more embodiments, a multi-enabled clock gating circuit having reduced clock enable setup time may be included in an integrated circuit for implementing clock gating during different operating modes of the integrated circuit.
REFERENCES:
patent: 5926487 (1999-07-01), Chappell et al.
patent: 2006/0041802 (2006-02-01), Grise et al.
Fischer Jeffrey Herbert
Goodall, III William James
Hamdan Fadi Adel
Barnie Rexford
Crawford Jason
Pauley Nicholas J.
QUALCOMM Incorporated
Rouse Thomas R.
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