Electronic digital logic circuitry – Multifunctional or programmable – Array
Patent
1995-06-02
1997-04-01
Westin, Edward P.
Electronic digital logic circuitry
Multifunctional or programmable
Array
326 21, 326 45, H03K 19177
Patent
active
056170416
ABSTRACT:
In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interconnect matrix wordline when the memory element is in a first state, and for blocking the macrocell output signal when the memory element is in a second state. This prevents coupling noise in the interconnect matrix because unnecessary feedback signals are prevented from entering the interconnect matrix. In another embodiment, a method is provided in which unused macrocells produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by a multiple concurrent switching event. In another embodiment, a sense amplifier is provided in which an EPROM shields coupling between wordlines and bitlines in an interconnect matrix.
REFERENCES:
patent: 4758746 (1988-07-01), Birkner
patent: 4789951 (1988-12-01), Birkner
patent: 5028821 (1991-07-01), Kaplinsky
patent: 5168177 (1992-12-01), Shankar
patent: 5300830 (1994-04-01), Hawes
"The Programmable Logic Data Book" copyright 1994, Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124, pp. 3-1 to 3-90.
Diba Sholeh
Ku Wei-Yi
Lee Napoleon W.
Nguyen Hy V.
Bever Patrick T.
Driscoll Benjamin D.
Harms Jeanette S.
Westin Edward P.
Xilinx , Inc.
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