Enhanced I/O control flexibility for generating control signals
Enhanced low voltage TTL interface
Enhanced low voltage TTL interface
Enhanced macrocell module for high density CPLD architectures
Enhanced macrocell module having expandable product term...
Enhanced passgate structures for reducing leakage current
Enhanced permutable switching network with multicasting...
Enhanced protection for input buffers of low-voltage flash...
Enhanced protection for input buffers of low-voltage flash...
Enhanced protection for input buffers of low-voltage flash...
Enhanced scheme to implement an interconnection fabric using...
Enhanced scheme to implement an interconnection fabric using...
Enhanced timing margin memory interface
EPLD chip with hybrid architecture optimized for both speed and
EPLD chip with hybrid architecture optimized for both speed and
Equal delay current-mode logic circuit
Equalization circuit cells with higher-order response...
Equalizing receiver with data to clock skew compensation
Erroneous operation protection circuit formed between data buses
Error correcting logic system