Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2005-09-06
2005-09-06
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S081000
Reexamination Certificate
active
06940310
ABSTRACT:
An input buffer is discussed that inhibits semiconductor breakdown of thin gate-oxide transistors in low-voltage integrated circuits. One aspect of the input buffer includes an input stage having a gate, a drain, and a source. The gate of the input stage is receptive to an inhibiting signal, and the drain is receptive to an input signal. The input stage inhibits the input signal from being presented at the source of the input stage when the inhibiting signal is at a predetermined level. The input buffer further includes an output stage having an inverter that includes a first connection and a second connection. The first connection couples to the source of the input stage, and the second connection presents the input signal to a low-voltage flash memory device.
REFERENCES:
patent: 5300835 (1994-04-01), Assar et al.
patent: 5543734 (1996-08-01), Volk et al.
patent: 5589783 (1996-12-01), McClure
patent: 5589790 (1996-12-01), Allen
patent: 5822267 (1998-10-01), Watanabe et al.
patent: 5852540 (1998-12-01), Haider
patent: 5880998 (1999-03-01), Tanimura et al.
patent: 5896400 (1999-04-01), Roohparvar et al.
patent: 5933026 (1999-08-01), Larsen et al.
patent: 5973900 (1999-10-01), Sher et al.
patent: 5999390 (1999-12-01), Cho et al.
patent: 6002627 (1999-12-01), Chevalier
patent: 6013932 (2000-01-01), Chevallier
patent: 6025737 (2000-02-01), Patel et al.
patent: 6031393 (2000-02-01), Wayner
patent: 6058063 (2000-05-01), Jang
patent: 6084430 (2000-07-01), Wayner
patent: 6121795 (2000-09-01), Curd et al.
patent: 6282145 (2001-08-01), Tran et al.
patent: 6333663 (2001-12-01), Lee
patent: 0831439 (1998-03-01), None
patent: 59224162 (1985-04-01), None
patent: WO-00/42615 (2000-07-01), None
“1.8 V 0.15 V (Normal Range), and 1.2—1.95 V (Wide Range) Power Supply Voltage and Interface Standard for Non-Terminated Digital Integrated Circuit”,EIA/JEDEC Standard, EIA/JESD8-7, Electronic Industries Association, Engineering Department,(1997),pp. 1-3.
“Overvoltage Protection Circuit”,IBM Technical Disclosure Bulletin, IBM Corp., New York, US, vol. 30, No. 12, XP002017155, (May 1, 1988).
“Test Method A114-A, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM)”,EIA/JEDEC Standard, EIA/JESD22-A114-A, Electronic Industries Association, Engineering Department,(1997),pp. 1-9.
“Test Method A115-A, Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM)”,EIA/JEDEC Standard, EIA/JESD22-A115-A, Electronics Industries Association, Engineering Department,(1997),pp. 1-9.
“Test Method C101, Field-Induced Charged-Device Model Test Method for Electrostatic Discharge Withstand Thresholds of Microelectronic Components”,JEDEC Standard, JESD22-C101, Electronic Industries Association, Engineering Department,(1995),pp. 1-6.
D'Ambrosio Elio
Marotta Giulio-Giuseppe
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