Enhanced timing margin memory interface

Details Enhanced timing margin memory interface Enhanced timing margin memory interface

2007-12-25

2007-12-25

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S104000, C327S170000

Reexamination Certificate

active

11206638

ABSTRACT:
The present invention is an electronic circuit that significantly enhances timing margin in high-speed, digital memory modules. The circuit is implemented is applicable to all switching waveforms on both control and data signal lines that drive the memory bus. Implementation of the present invention also provides a significant reduction in power dissipation compared to memory modules of comparable size and speed utilizing the present art.

REFERENCES:
patent: 6717479 (2004-04-01), Suda
patent: 7119549 (2006-10-01), Lee et al.

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