EPLD chip with hybrid architecture optimized for both speed and

Details EPLD chip with hybrid architecture optimized for both speed and EPLD chip with hybrid architecture optimized for both speed and

1994-04-28

1995-09-12

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 17, H03K 19177

Patent

active

054500214

ABSTRACT:
A hybrid EPLD (chip) architecture has multiple first blocks each including a first type programmable AND array and multiple first type macrocells which are complex in structure and highly configurable; and multiple blocks each including a second type programmable AND array having fewer input lines and product term output lines than does the first type AND array, and multiple second type macrocells which have fewer logic gates than do the first type macrocells. The EPLD has a programmable interconnect matrix for interconnecting all the blocks.

REFERENCES:
patent: 4758746 (1988-07-01), Birkner et al.
patent: 4870302 (1989-09-01), Freeman
patent: 5023484 (1991-06-01), Pathak et al.
patent: 5095523 (1992-03-01), Delaruelle et al.
patent: 5155389 (1992-10-01), Furtek

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