Tileable field-programmable gate array architecture

Tileable field-programmable gate array architecture

Tileable field-programmable gate array architecture

Time-multiplexed programmable logic devices

Transferring data in a parallel processing environment

Transferring data in a parallel processing environment

Transferring data in a parallel processing environment

Transparent data-triggered pipeline latch

Tri-statable input/output circuitry for programmable logic

Tri-Statable input/output circuitry for programmable logic

Tristate structures for programmable logic devices

Tristate structures for programmable logic devices

Tristate structures for programmable logic devices

Two-stage programmable interconnect architecture

Universal digital block interconnection and channel routing

Universal logic module with arithmetic capabilities

Universal logic module with arithmetic capabilities

Use of dangling partial lines for interfacing in a PLD

Use of dangling partial lines for interfacing in a PLD

User configurable on-chip memory system