Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2008-07-01
2008-07-01
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S041000, C326S047000
Reexamination Certificate
active
07394288
ABSTRACT:
An integrated circuit includes a plurality of tiles. Each tile includes a processor, a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles, and a switch memory that stores instruction streams that are able to operate independently for respective output ports of the switch.
REFERENCES:
patent: 6768336 (2004-07-01), Vishkin et al.
patent: 2004/0250046 (2004-12-01), Gonzalez et al.
patent: WO 2004/072796 (2004-08-01), None
Agarwal, Anant. “Raw Computation,”Scientific Americanvol. 281, No. 2: 44-47, Aug. 1999.
Taylor, Michael Bedford et. al., “Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams,”Proceedings of International Symposium on Computer Architecture,Jun. 2004.
Taylor, Michael Bedford et. al., “Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures,”Proceedings of the International Symposium on High Performance Computer Architecture,Feb. 2003.
Taylor, Michael Bedford et. al., “A 16-Issue Multiple-Program-Counter Microprocessor with Point-to-Point Scalar Operand Network,”Proceedings of the IEEE International Solid-State Circuits Conference,Feb. 2003.
Taylor, Michael Bedford et. al., “The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs,”IEEE Micro,pp. 25-35, Mar.-Apr. 2002.
Lee, Walter et. al., “Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,”Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems(ASPLOS-VIII), San Jose, CA, Oct. 4-7, 1998.
Kim, Jason Sungtae et. al., “Energy Characterization of a Tiled Architecture Processor with On-Chip Networks,”International Symposium on Low Power Electronics and Design,Seoul, Korea, Aug. 25-27, 2003.
Barua, Rajeev et. al., “Compiler Support for Scalable and Efficient Memory Systems,”IEEE Transactions on Computers,Nov. 2001.
Waingold, Elliot et. al., “Baring it all to Software: Raw Machines,”IEEE Computer,pp. 86-93, Sep. 1997.
Lee, Walter et. al., “Convergent Scheduling,”Proceedings of the 35thInternational Symposium on Microarchitecture, Istanbul, Turkey, Nov. 2002.
Wentzlaff, David and Anant Agarwal, “A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation,”MIT/LCS Technical Report LCS-TR-944,Apr. 2004.
Suh, Jinwoo et. al., “A Performance Analysis of PIM, Stream Processing , and Tiled Processing on Memory-Intensive Signal Processing Kernels,”Proceedings of the International Symposium on Computer Architecture,Jun. 2003.
Barua, Rajeev et. al., “Maps: A Compiler-Managed Memory System for Raw Machines,”Proceedings of the Twenty-Sixth International Symposium on Computer Architecture (ISCA-26),Atlanta, GA, Jun. 1999.
Barua, Rajeev et. al., “Memory Bank Disambiguation using Modulo Unrolling for Raw Machines,”Proceedings of the Fifth International Conference on High Performance Computing,Chennai, India, Dec. 17-20, 1998.
Agarwal, A. et. al., “The Raw Compiler Project,”Proceedings of the Second SUIF Compiler Workshop,Stanford, CA, Aug. 21-23, 1997.
Taylor, Michael. The Raw Prototype Design Document V5.01 [online]. Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Sep. 6, 2004 [retrieved on Sep. 25, 2006]. Retrieved from the Internet: <ftp://ftp.cag.lcs.mit.edu/pub/raw/documents/RawSpec99.pdf>.
Moritz, Csaba Andras et. al., “Hot Pages: Software Caching for Raw Microprocessors,”MIT/LCS Technical Memo LCS-TM-599,Aug. 1999.
Fish & Richardson P.C.
Massachusetts Institute of Technology
Tran Anh Q
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