Periphery input/output interconnect structure

Details Periphery input/output interconnect structure Periphery input/output interconnect structure

1995-10-16

1997-06-24

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326101, H03K 19177

Patent

active

056420587

ABSTRACT:
A mechanism is provided for allowing input/output signal routing along the periphery of a programmable integrated circuit (IC) so that uniform circuit usage across the programmable integrated circuit is allowed in conjunction with predetermined pin assignments. The mechanism includes a plurality of periphery interconnect lines that run along the periphery of a programmable IC. Input/output blocks (IOBs) that are similarly along the periphery of the programmable IC and configurable logic blocks (CLBs) are coupled to the plurality of periphery interconnect lines using a programmable local interconnect structure. Each IOB includes an associated pad and an input/output external pin. Individual segments of the plurality of periphery interconnect lines utilize a bi-directional buffer to buffer a line of the periphery interconnect. Uniform buffered segments of the periphery interconnect are disposed such that for an interconnect of n lines, each line of the periphery interconnect is buffered at least once every n segments. In operation, a CLB located away from the periphery of the IC can output a signal over the local interconnect, onto the plurality of periphery interconnect lines, onto another local interconnect, into an IOB and over its external pin. To input a signal, the path is reversed. The pin and the CLB do not need to be adjacent.

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Babb, Jonathan; Tessier, Russell; and Agarwal, Anant, "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators", IEEE Workshop on FPGAs for Custom Computing Machines, FCCM 93, Apr. 5-7, 1993 pp. 1-15.

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