Periphery clock signal distribution circuitry for structured...

Details Periphery clock signal distribution circuitry for structured... Periphery clock signal distribution circuitry for structured...

2008-05-28

2009-11-24

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S039000, C326S047000

Reexamination Certificate

active

07622952

ABSTRACT:
A structured ASIC device includes highly flexible clock signal routing to peripheral IO circuitry of the device. A plurality of peripheral IO circuits are divided into subpluralities of adjacent ones of those circuits. Each subplurality has associated clock signal routing that is mask-programmable to supply any of a plurality of clock signals to any of the IO circuits in the subplurality. Core circuitry of the structured ASIC includes clock signal distribution circuitry, and that distribution circuitry can supply (via buffers associated with each subplurality) the same plurality of clock signals to the routing circuitry associated with all of the subpluralities.

REFERENCES:
patent: 6886143 (2005-04-01), Park
patent: 7243329 (2007-07-01), Chua et al.
patent: 7275232 (2007-09-01), Schleicher et al.
patent: 2005/0041149 (2005-02-01), Chan et al.
patent: 2006/0267661 (2006-11-01), Lim et al.

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