Reduced computation digital filter

Reduced computation system for wavelet transforms

Reduced gate count differentiator

Reduced hardware linear interpolator

Reduced multiplier digital IIR filters

Reduced power matched filter using precomputation

Reduced product term carry chain

Reduced-hardware soft error detection

Reduced-latency floating-point pipeline using normalization shif

Reduced-width low-error multiplier

Reducing peak spectral error in inverse Fast Fourier Transform u

Reducing the hardware cost of a bank of multipliers by combining

Reduction of add-pipe logic by operand offset shift

Reduction of digital filter delay

Reduction of execution times for convolution operations

Reduction of periodic signals in pseudo-random noise...

Redundancy-free circuits for zero counters

Refinement of interpolated signals

Reflection filter

Reforming process having a high selectivity and activity for deh