Reducing the hardware cost of a bank of multipliers by combining

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

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708319, G06F 752

Patent

active

061416746

ABSTRACT:
A circuit that performs the function of a bank of multipliers while reducing hardware costs includes shared term generator that generates a set of shared terms in response to an input value. The circuit further includes a set of combining circuits each of which generates a result term by combining one or more of the shared terms so that the result term equals the input value multiplied by a corresponding data value. The circuit generates the share terms once and then reuses the shared terms in differing combining circuits as needed thereby eliminating duplication of terms and associated implementation hardware.

REFERENCES:
patent: 4745570 (1988-05-01), Diedrich et al.
patent: 4799183 (1989-01-01), Nakano et al.
patent: 5646877 (1997-07-01), Mahant-Shetti et al.
patent: 5680335 (1997-10-01), Ikeyama et al.
patent: 5781462 (1998-07-01), Yamanaka et al.

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